Integrated circuits in microelectronic devices are becoming smaller in order to provide higher performance for products requiring advanced technology. The integrated circuits are comprised of several layers which are individually formed with a unique pattern. In certain layers, shallow trench isolation (STI) structures are needed to separate areas where active devices are to be formed. The process typically involves forming a trench between areas where active devices will be located and filling the trench in a high density plasma (HDP) chemical vapor deposition (CVD) process with a dielectric material that will insulate neighboring devices and prevent unwanted “crosstalk” between wiring. Dielectric materials with a relatively high dielectric constant (k) such as silicon dioxide with a k value of about 4 are no longer acceptable. A dielectric material with a k value of 3.5 or less and preferably 3 or less is needed for STI structures that have sub-micron dimensions, especially those that have a width which is smaller than about 0.5 microns.
For metal-oxide-semiconductor (MOS) devices based on a local oxidation of silicon (LOCOS) technology as shown in FIG. 1, the parasitic capacitance includes a junction capacitance (Cj) and a sidewall capacitance (Cjsw). Substrate 10 is typically doped or undoped silicon. In this case, substrate 10 includes a well region 11 and a source/drain (S/D) region 12. A LOCOS oxide structure 13 is formed on one side of the S/D region 12. On the opposite side of the S/D region 12, a gate dielectric layer 14, a gate electrode 15, and a spacer 16 are illustrated. For the structure depicted in FIG. 1, the Cjsw is mainly attributed to the junction interface between S/D region 12 and well region 11. Cjsw is bias dependent because the depletion width near the junction interface will widen for higher junction voltage.
An improved isolation technology has been developed for trench widths of approximately 0.5 microns or less. The newer shallow trench isolation (STI) structure pictured in FIG. 2 comprises a substrate 20, a well region 21, a S/D region 22, and another device or well pick-up region 23. A STI feature containing a barrier liner 24 and a dielectric layer 25 is located adjacent to the S/D region 22. On the opposite side of the S/D region 22 is a gate dielectric layer 26 and a gate electrode 27 that has a sidewall spacer 28. It is believed that the sidewall capacitance across the material in the STI feature might be more significant than the depletion region around the junction interface between S/D region 22 and well region 21. In the STI structure, Csw1 refers to capacitance between neighboring devices while Csw2 is the edge capacitance between device (S/D region 22) and substrate 20.
The sidewall capacitance (Csw) which is equivalent to Csw1+Csw2 for the STI structure in FIG. 2 is plotted in FIG. 3 as a function of applied voltage. The measured Csw in (Farad/m) decreases slightly as voltage is increased. In this example, the voltage is monitored between the S/D region 22 (n+state) and a p-well 21. Region 23 represents a p+ pick-up. Note that Csw is nearly independent of voltage.
Sidewall capacitance is a very important factor to be reckoned with in advanced technology. As device integration is enhanced and STI width is reduced further, Csw will rise dramatically and thus degrade circuit speed. The illustration in FIG. 4 shows how sidewall capacitance increases by over 50% when reducing a STI width from 0.5 microns (curve 36), to 0.24 microns (curve 35). For common devices with small sizes in digital circuits, Csw might account for more than 50% of the total parasitic capacitance within the source and drain. Therefore, a new STI structure is needed to counteract this trend of increasing Csw.
In U.S. Pat. No. 5,702,976, a shallow trench that is less than 250 nm in depth to minimize parasitic interdevice currents and void formation is filled with a low k dielectric material which is preferably halide doped SiO2. A barrier layer comprised of an oxide or nitride is deposited on the walls and bottom of the trench prior to filling with a low k dielectric material. No cap layer is included.
Low k dielectric layers such as carbon doped silicon oxide are porous and must be densified by a plasma treatment that also prevents moisture uptake. An example of a post-deposition treatment that stabilizes a low k dielectric film is found in U.S. Pat. No. 6,436,808 and involves a nitrogen plasma that can additional include NH3. The plasma treatment is believed to form a thin skin of silicon nitride or silicon oxynitride having a thickness of about 20 to 50 Angstroms.
U.S. Pat. No. 6,140,691 describes a trench isolation structure that has a low k dielectric material totally encapsulated within an oxide liner in a trench. The dielectric material is preferably a fluorinated oxide or polymer. A channel stop dopant is implanted in the trench before the oxide liner is deposited. However, the trench is still comprised of a significant amount of oxide because of a relatively thick oxide cap.
AMD also teaches the use of a low k dielectric layer between an oxide liner and an oxide filler in a STI feature in U.S. Pat. No. 5,943,585. Here the percentage of low k material in the trench is less than the previous case. Similarly, the percentage of a low k dielectric material in a STI structure is minimal in U.S. Pat. No. 6,087,705 where the low k material is restricted to sidewall spacers at the edge of the trench structure.
In yet another variation of the AMD trench structure, a method is described in U.S. Pat. No. 5,811,347 for performing a nitrogen implant in an oxide liner. The nitrogen containing liner forms a stronger bond to the silicon sidewalls of the trench and ties up “dangling” silicon bonds that might otherwise contribute to a leakage current. The modified trench liner contains about 0.5 to 2% nitrogen.
Another method of forming an STI structure is described in U.S. Pat. No. 6,344,415. Trenches are formed by patterning a mask on an amorphous silicon layer that is deposited on a pad oxide layer. The pattern is etched through the α-Si layer and pad oxide into the substrate. Then the trench is filled with an oxide liner and an insulation material before a chemical mechanical polish (CMP) step planarizes the surface.